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nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram 1 rev 1.0 may, 2001 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. features ? high performance: ? single pulsed ras interface ? fully synchronous to positive clock edge ? four banks controlled by ba0/ba1 (bank select) ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8 ? programmable wrap: sequential or interleave ? multiple burst read with single write option ? automatic and controlled precharge command ? data mask for read/write control (x4, x8) ? dual data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? standard power operation ? 8192 refresh cycles/64ms ? random column address every ck (1-n rule) ? single 3.3v 0.3v power supply ? lvttl compatible ? package: 54-pin 400 mil tsop-type ii ? -7k parts for pc133 2-2-2 operation -75b parts for pc133 3-3-3 operation -8b parts for pc100 2-2-2 operation description the nt5sv64m4at, nt5sv32m8at, and nt5sv16m16at are four-bank synchronous drams organized as 16mbit x 4 i/o x 4 bank, 8mbit x 8 i/o x 4 bank, and 4mbit x 16 i/o x 4 bank, respectively. these synchronous devices achieve high-speed data transfer rates of up to 133mhz by employing a pipeline chip architecture that synchronizes the output data to a system clock. the chip is fabricated with ntc?s advanced 256mbit single transistor cmos dram process technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, and data input/out- put (i/o or dq) circuits are synchronized with the positive edge of an externally supplied clock. ras , cas , we , and cs are pulsed signals which are exam- ined at the positive edge of each externally applied clock (ck). internal chip operating modes are defined by combina- tions of these signals and a command decoder initiates the necessary timings for each operation. a fifteen bit address bus accepts address data in the conventional ras / cas mul- tiplexing style. thirteen row addresses (a0-a12) and two bank select addresses (ba0, ba1) are strobed with ras . eleven column addresses (a0-a9, a11) plus bank select addresses and a10 are strobed with cas . column address a11 is dropped on the x8 device, and column addresses a11 and a9 are dropped on the x16 device. prior to any access operation, the cas latency, burst length, and burst sequence must be programmed into the device by address inputs a0-a12, ba0, ba1 during a mode register set cycle. in addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gap- less data rate of up to 133mhz is possible depending on burst length, cas latency, and speed grade of the device. auto refresh (cbr) and self refresh operation are sup- ported. -7k 3 cl=2 -75b, cl=3 -8b, cl=2 units f ck clock frequency 133 133 100 mhz t ck clock cycle 7.5 7.5 10 ns t ac clock access time 1 ? ? ? ns t ac clock access time 2 5.4 5.4 6 ns 1. terminated load. see ac characteristics on page 37. 2. unterminated load. see ac characteristics on page 37 . 3. t rp = t rcd = 2 cks
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 2 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. pin assignments for planar components (top view) 54-pin plastic tsop(ii) 400 mil 16m bit x 4 i/o x 4 bank nt5sv64m4at 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc v dd nc nc nc we cas ras cs ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc v ss nc nc nc dqm ck cke a12 a11 a9 23 24 25 32 31 30 a10/ap a0 a1 a2 a8 a7 a6 a5 26 27 29 28 a3 v dd a4 v ss v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc v dd nc dq2 nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc v ss nc dq5 nc dqm ck cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 v dd dq3 dq4 ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 v ss dq12 dq11 nc udqm ck cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 4m bit x 16 i/o x 4 bank nt5sv16m16at 8m bit x 8 i/o x 4 bank nt5sv32m8at
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 3 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. pin description ck clock input dq0-dq15 data input/output cke (cke0, cke1) clock enable dqm, ldqm, udqm data mask cs chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+3.3v) we write enable v ssq ground for dqs ba1, ba0 bank select nc no connection a0 - a1 2 address inputs ? ? input/output functional description symbol type polarity function ck input positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke, cke0, cke1 input active high activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs input active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we input active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. ba1, ba0 input ? selects which bank is to be active. a0 - a12 input ? during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sam- pled at the rising clock edge. during a read or write command cycle, a0-a9 and a11 defines the column address (ca0-ca9, ca11), when sampled at the rising clock edge. assume the x4 organization. a10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. if a10 is high, auto-precharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if a10 is high, all banks will be precharged regardless of the state of bs. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. dq0 - dq15 input- output ? data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in x16 products, the ldqm and udqm control the lower and upper byte i/o buffers, respectively. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. dqm low turns the output buffers on and dqm high turns them off. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. v dd , v ss supply ? power and ground for the input buffers and the core logic. v ddq v ssq supply ? isolated power supply and ground for the output buffers to provide improved noise immunity.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 4 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ordering information organization part number speed grade package self refresh clock frequency@cas latency note 64m x 4 nt5sv64m4at-7k 143mhz@cl3 133mhz@cl2 pc133 , pc100 400mil 54- pin tsop ii sp nt5sv64m4at-75b 133mhz@cl3 100mhz@cl2 pc133 , pc100 nt5sv64m4at-8b 125mhz@cl3 100mhz@cl2 pc100 32m x 8 nt5sv32m8at-7k 143mhz@cl3 133mhz@cl2 pc133 , pc100 nt5sv32m8at-75b 133mhz@cl3 100mhz@cl2 pc133 , pc100 NT5SV32M8AT-8B 125mhz@cl3 100mhz@cl2 pc100 16m x 16 nt5sv16m16 at -7k 143mhz@cl3 133mhz@cl2 pc133 , pc100 nt5sv16m16 a t -75b 133mhz@cl3 100mhz@cl2 pc133 , pc100 nt5sv16m16 a t -8b 125mhz@cl3 100mhz@cl2 pc100 16m x 16 nt5sv16m16 a t -7kl 143mhz@cl3 133mhz@cl2 pc133 , pc100 lp nt5sv16m16 a t -75bl 133mhz@cl3 100mhz@cl2 pc133 , pc100 nt5sv16m16 a t -8bl 125mhz@cl3 100mhz@cl2 pc100 sp : standard power ; lp : low power
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 5 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. block diagram dq 0 dq x d a t a i n p u t / o u t p u t b u f f e r s cke buffer ck b uffer cke ck cs ras cas dqm we c o m m a n d d e c o d e r m o d e r e g i s t e r c o u n t e r c o l u m n a d d r e s s c o u n t e r r e f r e s h a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 sense amplifiers memory bank 1 cell array r o w d e c o d e r a d d r e s s b u f f e r s ( 1 5 ) column decoder sense amplifiers memory bank 3 cell array r o w d e c o d e r column decoder sense amplifiers memory bank 0 cell array r o w d e c o d e r column decoder sense amplifiers memory bank 2 cell array r o w d e c o d e r column decoder d a t a c o n t r o l c i r c u i t r y ba0 ba1 c o n t r o l s i g n a l g e n e r a t o r cell array, per bank, for 16m b x 4 dq: 8192 r ow x 2048 c ol x 4 dq (dq0-dq3). cell array, per bank, for 8m b x 8 dq: 8192 r ow x 1024 c ol x 8 dq (dq0-dq7). cell array, per bank, for 4m b x 16 dq: 8192 r ow x 512 c ol x 16 dq (dq0-dq15). a1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 6 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initializa - tion sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. the ck signal must be started at the same time. after power on, an initial pause of 200 m s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to ini- tialize the mode register. a minimum of two auto refresh cycles (cbr) are also required. these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register for application flexibility, cas latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the sdram mode register with a single mode register set command. any content of the mode register can be altered by re-executing the mode register set command. if the user chooses to modify only a subset of the mode register variables, all four variables must be redefined when the mode register set command is issued. after initial power up, the mode register set command must be issued before read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs , and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. cas latency the cas latency is a parameter that is used to define the delay from when a read command is registered on a rising clock edge to when the data from that read command becomes available at the outputs. the cas latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. the value of the cas latency is determined by the speed grade of the device and the clock frequency that is used in the application. a table showing the relationship between the cas latency, speed grade, and clock frequency appears in the electrical characteristics section of this document. once the appropriate cas latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see programming the mode register in the previous section.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 7 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. mode register operation (address input for mode set) a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bt burst length cas latency mode cas latency m6 m5 m4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length m2 m1 m0 length sequential interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved burst type m3 type 0 sequential 1 interleave operation mode m1 4 m1 3 m12 m11 m10 m9 m8 m7 mode 0 0 0 0 0 0 0 0 normal 0 0 0 0 0 1 0 0 multiple burst wit h s ingle write operation mode ba0 ba1 bus (ax) register(mx) a12
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 8 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). there are three parameters that define how the burst mode will operate. these parameters include burst sequence, burst length, and operation mode. the burst sequence and burst length are programmable, and are determined by address bits a0 - a3 during the mode register set command. operation mode is also programmable and is set by address bits a7 - a12, ba0, and ba1. the burst type is used to define the order in which the burst data will be delivered or stored to the sdram. two types of burst sequences are supported, sequential and interleaved. see the table below. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organi- zation: x4, x8, or x16). burst operation mode can be normal operation or multiple burst with single write operation. normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. multiple burst w ith single write operation was added to support write through cache operation. here, the programmed burst length only applies to read cycles. all write cycles are single write operations when this mode is selected. note: page length is a function of i/o organization and column addressing. x4 organization (ca0-ca9, ca11); page length = 2048 bits x8 organization (ca0-ca9); page length = 1024 bits x16 organization (ca0-ca8); page length = 512 bits burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 9 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. bank activate command in relation to the operation of a fast page mode dram, the bank activate command correlates to a falling ras signal. the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank select address ba0 - ba1 is used to select the desired bank. the row address a0 - a12 is used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. the delay from when the bank activate command is applied to when the first read or write operation can begin must meet or exceed the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the minimum time interval between successive bank activate commands to the same bank is deter- mined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras(max) . bank select the bank select inputs, ba0 and ba1, determine the bank to be used during a bank activate, precharge, read, or write oper- ation. bank activate command cycle bank selection bits ba0 ba1 bank 0 0 bank 0 1 0 bank 1 0 1 bank 2 1 1 bank 3 address ck t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command nop nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate ras - cas delay ( t rcd ) : ?h? or ?l? ras cycle time ( t rc ) precharge ras - ras delay time ( t rrd ) bank b row addr. ( cas latency = 3, t rcd = 3)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 10 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high and cas low at the clock?s rising edge after the necessary ras to cas delay (t rcd ). we must also be defined at this time to determine whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the start- ing column address. the sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles up to 133mhz. the number of serial data bits for each access is equal to the burst length, which is programmed into the mode register. similar to page mode of conventional drams, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. the refresh period (t ref ) is what limits the number of random column accesses to an activated bank. a new burst access can be done even before the previous burst ends. the ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-n rule. when the previous burst is interrupted by another read or write com- mand, the remaining addresses are overridden by the new address. precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. to perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new bank acti- vate command must be issued. when more than one bank is activated, interleaved (ping pong) bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. when multiple banks are acti- vated, column to column interleave operation can be done between different pages. finally, read or write commands can be issued to the same bank or between active banks on every clock cycle.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 11 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst, the mode register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). the delay from the start of the command to when the data from the first cell appe ars on the outputs is equal to the value of the cas latency that is set in the mode register. read interrupted by a read a burst read may be interrupted before completion of the burst by another read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. when the previous burst is interrupted, the remain- ing addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied, at this point the data from the interrupting read command appears. burst read operation read interrupted by a read command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3 , dqs cas latency = 3 dout a 1 dout a 2 dout a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2 , dqs dout a 0 dout a 1 dout a 2 dout a 3 (burst length = 4, cas latency = 2, 3) command read a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 (burst length = 4, cas latency = 2, 3)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 12 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first or second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus. minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 : ?h? or ?l? din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop (burst length = 4, cas latency = 2, 3) dqm high for cas latency = 2 only. required to mask first bit of read data.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 13 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. non-minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop cl = 3: dqm needed to mask first bit of read data. cl = 2: dqm needed to mask first, second bit of read data. (burst length = 4, cas latency = 2, 3) : dqm high for cas latency = 2 : dqm high for cas latency = 3
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 14 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst write command the burst write command is initiated by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. there is no cas latency required for burst write cycles. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. when the burst has fin- ished, any additional data supplied to the dq pins will be ignored. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is inter- rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro- grammed burst length is satisfied. burst write operation write interrupted by a write command nop write a nop nop nop nop nop nop dqs din a 0 din a 1 din a 2 din a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is masked. the first data element and the write are registered on the same clock edge. ( burst length = 4, cas latency = 2, 3) : ?h? or ?l? command nop write a write b nop nop nop nop nop dqs din a 0 din b 0 din b 1 din b 2 nop din b 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 1 ck i nterval (burst length = 4, cas latency = 2, 3)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 15 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is registered. the dqs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. when the read command is registered, any residual data from the burst write cycle will be ignored. data that is pre- sented on the dq pins before the read command is initiated will actually be written to the memory. minimum write to read interval command nop write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 (burst length = 4, cas latency = 2, 3) : ?h? or ?l?
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 16 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. non-minimum write to read interval command write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 nop din a 1 din a 1 (burst length = 4, cas latency = 2, 3) : ?h? or ?l?
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 17 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst opera- tion is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is engaged. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. regardless of burst length, the precharge will begin ( cas latency - 1) clocks prior to the last data output. auto-precharge can also be implemented during write commands. a read or write command without auto-precharge can be terminated in the midst of a burst operation. however, a read or write command with auto-precharge cannot be interrupted by a command to the same bank. therefore use of a read, write, or precharge command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper- ation is completed. once the precharge operation has started the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. when using the auto-precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras(min) . if this interval does not satisfy t ras(min) then t rcd must be extended. burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge * bank can be reactivated at completion of t rp . dout a 0 dout a 0 nop ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 1, cas latency = 2, 3)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 18 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst read with auto-precharge burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 0 nop dout a 1 dout a 1 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2, 3) command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 1 dout a 2 dout a 3 nop dout a 0 dout a 1 dout a 2 dout a 3 * b ank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 4, cas latency = 2, 3)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 19 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. although a read command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a read or write command to a different bank. if the command is issued before auto-precharge begins then the precharge function will begin with the new command. the bank being auto-precharged may be reactivated after the delay t rp . if interrupting a read command with auto-precharge with a write command, dqm must be used to avoid dq contention. burst read with auto-precharge interrupted by read burst read with auto-precharge interrupted by write t rp ? command nop nop nop nop read a auto-precharge ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t rp ? t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 * b ank can be reactivated at completion of t rp . dout a 0 dout a 1 nop dout a 0 dout a 1 dout b 0 dout b 1 read b dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 ? t rp is a function of c lock cycle time and speed sort. see the clock frequency and latency table. * * (burst length = 4, cas latency = 2, 3) command nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t ck2, dqs cas latency = 2 dqm nop dout a 0 d in b 0 d in b 1 write b d in b 2 d in b 3 nop d in b 4 * ba nk can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. . see the clock frequency and latency table . * (burst length = 8, cas latency = 2)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 20 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. if a10 is high when a write command is issued, the write with auto-precharge function is initiated. the bank undergoing auto- precharge cannot be reactivated until t dal , data-in to active delay, is satisfied. similar to the read command, a write command with auto-precharge can not be interrupted by a command to the same bank. it can be interrupted by a read or write command to a different bank, however. the interrupting command will terminate the write. the bank undergoing auto-precharge can not be reactivated until t dal is satisfied. burst write with auto-precharge burst write with auto-precharge interrupted by write din a 0 command nop nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop din a 0 din a 1 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop nop nop * bank can be reactivated at completion of t dal . t dal ? t dal ? * * (burst length = 2, cas latency = 2, 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort. din a 0 command nop nop nop write a auto-precharge din a 1 t dal ? ck t0 t1 t2 t3 t4 t5 nop t ck3, dqs cas latency = 3 write b din b 0 din b 1 din b 2 din b 3 t6 t7 t8 nop nop nop * b ank can be reactivated at completion of t dal . * (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 21 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras , and we are low and cas is high at the rising edge of the clock. the precharge command can be used to pre- charge each bank separately or all banks simultaneously. three address bits, a10, ba0, and ba1, are used to define which bank(s) is to be precharged when the command is issued. for read cycles, the precharge command may be applied ( cas latency - 1) prior to the last data output. for write cycles, a delay must be satisfied from the start of the last burst write cycle until the precharge command can be issued. this delay is known as t dpl , data-in to precharge delay. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the pre- charge time (t rp ). burst write with auto-precharge interrupted by read bank selection for precharge by address bits a10 bank select precharged bank(s) low ba0, ba1 single bank defined by ba0, ba1 high don?t care all banks din a 0 command nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop * t ck3 , dqs cas latency = 3 bank a can be reactivated at completion of t dal . * read b din a 2 nop dout b 0 dout b 1 dout b 2 t dal ? (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 22 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst read followed by the precharge command burst write followed by the precharge command command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t rp bank a can be reactivated at completion of t rp . * * (burst length = 4, cas latency = 3) ? ? t rp is a function of clock cycle and speed sort. command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 0 din ax 1 bank can be reactivated at completion of t rp . * activate bank ax t ck2, dqs cas latency = 2 t dpl ? * t rp ? precharge a ? t dpl and t rp are functions of clock cycle and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 23 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. precharge termination the precharge command may be used to terminate either a burst read or burst write operation. when the precharge command is issued, the burst operation is terminated and bank precharge begins. for burst read operations, valid data will continue to appear on the data bus as a function of cas latency. burst read interrupted by precharge command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 2 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t ck3 , dqs cas latency = 3 dout ax 0 dout ax 1 dout ax 2 dout ax 3 t rp ? t rp ? * * bank a can be reactivated at completion of t rp . * see the clock frequency and latency table. (burst length = 8, cas latency = 2, 3) ? t rp is a function of clock cycle time and speed sort.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 24 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst write operations will be terminated by the precharge command. the last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the precharge command equal to the data-in to precharge delay, t dpl . precharge termination of a burst write command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 din ax 2 t dpl ? din ax 0 t ck2 , dqs cas latency = 2 nop din ax 1 din ax 2 din ax 0 t ck3 , dqs cas latency = 3 dqm precharge a ? t dpl is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. (burst length = 8, cas latency = 2, 3) t dpl ?
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 25 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. automatic refresh command ( cas before ras refresh) when cs , ras , and cas are held low with cke and we high at the rising edge of the clock, the chip enters the automatic refresh mode (cbr). all banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto refresh command (cbr) can be applied. an address counter, internal to the device provides the address during the refresh cycle. no control of the external address pins is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto refresh command (cbr) and the next activate command or subsequent auto refresh command must be greater than or equal to the ras cycle time (t rc ). self refresh command the sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by hav- ing cs , ras , cas , and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the user may halt the external clock while the device is in sel f refresh mode, however, the clock must be restarted before the device can exit self refresh operation. once the clock is cycling, the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the devic e exits self refresh operation and before the next command can be issued. this delay is equal to the ras cycle time (t rc ) plus the self refresh exit time (t srex ).
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 26 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. power down mode in order to reduce standby power consumption, two power down modes are available: precharge and active power down mode. to enter precharge power down mode, all banks must be precharged and the necessary precharge delay (t rp ) must occur before the sdram can enter the power down mode. if a bank is activated but not performing a read or write operation, active power down mode will be entered. (issuing a power down mode command when the device is performing a read or write operation causes the device to enter clock suspend mode. see the following clock suspend section.) once the power down mode is initiated by holding cke low, all of the receiver circuits except cke are gated off. the power down mode does not perform any refresh operations, therefore the device can?t remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command (or device deselect command) is required on the next rising clock edge. power down mode exit timing command nop command nop nop nop nop nop cke : ?h? or ?l? ck tm tm+2 tm+1 tm+3 tm+4 tm+5 tm+6 tm+7 tm+ 8 t ces(min) t ck
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 27 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. data mask the sdram has a data mask function that can be used in conjunction with data read and write cycles. when the data mask is activated (dqm high) during a write cycle, the write operation is prohibited immediately (zero clock latency). if the data mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of cas latency. no operation command the no operation command should be used in cases when the sdram is in an idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation com- mand will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t cares. data mask activated during a read cycle command nop read a nop nop nop nop nop nop nop dqm : ?h? or ?l? a two-clock delay before the dqs become hi-z dqs ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 (burst length = 4, cas latency = 2)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 28 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock suspend mode during normal access mode, cke is held high, enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends or ?freezes? any clocked operation that was currently being executed. there is a one-clock delay between the registration of cke low and the time at which the sdram?s operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited. when the operation of the sdram is suspended during the execution of a burst read operation, the last valid data output onto the dq pins will be actively held valid until clock suspend mode is exited. if clock suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the clock sus- pend mode is exited. clock suspend during a read cycle clock suspend during a write cycle ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop read a nop nop nop nop cke dqs dout a 0 dout a 2 dout a 1 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command dout element at the dqs when the suspend operation starts is held valid (burst length = 4, cas latency = 2) ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop write a nop nop nop nop cke dqs din a 2 din a 3 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command din is masked during the clock suspend period din a 1 din a 0 (burst length = 4, cas latency = 2)
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 29 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. command truth table (see note 1) function device state cke cs ras cas we dqm ba0 , ba1 a10 a12, a11 , a 9-a0 notes previous cycle current cycle mode register set idle h x l l l l x op code auto (cbr) refresh idle h h l l l h x x x x entry self refresh idle h l l l l h x x x x exit self refresh idle (self- refresh) l h h x x x x x x x l h h h single bank precharge see current state table h x l l h l x bs l x 2 precharge all banks see current state table h x l l h l x x h x bank activate idle h x l l h h x bs row address 2 write active h x l h l l x bs l column 2 write with auto-precharge active h x l h l l x bs h column 2 read active h x l h l h x bs l column 2 read with auto-precharge active h x l h l h x bs h column 2 reserved h x l h h l x x x x no operation any h x l h h h x x x x device deselect any h x h x x x x x x x clock suspend mode entry active h l x x x x x x x x 4 clock suspend mode exit active l h x x x x x x x x data write/output enable active h x x x x x l x x x 5 data mask/output disable active h x x x x x h x x x power down mode entry idle/active h l h x x x x x x x 6, 7 l h h h power down mode exit any (power down) l h h x x x x x x x 6, 7 l h h h 1. all of the sdram operations are defined by states of cs , we , ras , cas , and dqm at the positive rising edge of the clock. refer to the current state truth table. 2. bank select (ba0, ba1): ba0, ba1 = 0,0 selects bank 0; ba0, ba1 = 1,0 s elects bank 1; ba0, ba1 = 0,1 s elects bank 2; ba0, ba1 = 1,1 selects bank 3. 3. not applicable. 4. during normal access mode, cke is held high and ck i s enabled. when it is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes high at a clock timing t he data outputs are disabled and become high impedance after a two-clock delay. dqm also provides a data mask function for write cy cles. when it activates, the write operation at the clock is prohibited (zero clock latency). 6. all banks must be precharged before entering the power down mode. (if this command is issued during a burst operation, the devic e state will be clock suspend mode.) the power down mode does not perform any refresh operations; therefore the device can?t remai n in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. 7. a no operation or device deselect command is required on the next clock edge following cke going high .
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 30 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock enable (cke) truth table current state cke command action notes previous cycle current cycle cs ras cas we ba0 , ba1 a1 2 - a0 self refresh h x x x x x x x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l x x x x x x maintain self refresh power down h x x x x x x x invalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l x x x x x x maintain power down mode all banks idle h h h x x x refer to the idle state section of the current state truth table 3 h h l h x x 3 h h l l h x 3 h h l l l h x x cbr refresh h h l l l l op code mode register set 4 h l h x x x refer to the idle state section of the current state truth table 3 h l l h x x 3 h l l l h x 3 h l l l l h x x entry self refresh 4 h l l l l l op code mode register set l x x x x x x x power down 4 any state other than listed above h h x x x x x x refer to operations in the current state truth table h l x x x x x x begin clock suspend next cycle 5 l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. the minimum setup time for cke (t ces ) must be satisfied. when exiting power down mode, a nop command (or device deselect command) is required on the first rising clock after cke goes high (see page 26). 3. the address inputs d epend on the command that is issued. see the idle state section of the current state truth table for more informa- tion. 4. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idle stat e. 5. must be a legal command as defined in the current state truth table.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 31 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. current state truth table (part 1 of 3) (see note 1) current state command action notes cs ras cas we ba0 , ba1 a1 2 - a0 description idle l l l l op code mode register set set the mode register 2 l l l h x x auto or self refresh start auto or self refresh 2, 3 l l h l bs x precharge no operation l l h h bs row address bank activate activate the specified bank and row l h l l bs column write w/o precharge illegal 4 l h l h bs column read w/o precharge illegal 4 l h h h x x no operation no operation h x x x x x device deselect no operation or power down 5 row active l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge precharge 6 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto precharge 7, 8 l h l h bs column read start read; determine if auto precharge 7, 8 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start the write cycle 8, 9 l h l h bs column read terminate burst; start a new read cycle 8, 9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start a new write cycle 8, 9 l h l h bs column read terminate burst; start the read cycle 8, 9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the co mmand is being applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) refresh operation, if cke is inactive (low) than the self refresh mo de is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank no t being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 32 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. read with auto pre- charge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst precharging l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge no operation; bank(s) idle after t rp l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp row activating l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4, 10 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd current state truth table (part 2 of 3) (see note 1) current state command action notes cs ras cas we ba0 , ba1 a1 2 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the co mmand is being applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) refresh operation, if cke is inactive (low) than the self refresh mo de is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank no t being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 33 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. write recovering l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto precharge 9 l h l h bs column read start read; determine if auto precharge 9 l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl write recovering with auto pre- charge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4, 9 l h l h bs column read illegal 4, 9 l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl refreshing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal l h l h bs column read illegal l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc mode register accessing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal l h l h bs column read illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles current state truth table (part 3 of 3) (see note 1) current state command action notes cs ras cas we ba0 , ba1 a1 2 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the co mmand is being applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) refresh operation, if cke is inactive (low) than the self refresh mo de is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank no t being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 34 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v 1 v ddq power supply voltage for output -0.3 to +4.6 v 1 v in input voltage -0.3 to v dd +0.3 v 1 v out output voltage -0.3 to v dd +0.3 v 1 t a operating temperature (ambient) 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress r at- ing only and functional operation of the device at these or any other conditions above those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions (t a = 0 c to 70 c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ddq supply voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 ? v dd + 0.3 v 1, 2 v il input low voltage -0.3 ? 0.8 v 1, 3 1. all voltages referenced to v ss and v ssq . 2. v ih (max) = v dd + 1.2v for pulse width 5ns . 3. v il (min) = v ss - 1.2v for pulse width 5ns . capacitance (t a = 25 c, f = 1mhz, v dd = 3.3v 0.3v) symbol parameter min. typ max . units notes c i input capacitance (a0-a1 2, ba0, ba1, cs , ras , cas , we , cke, dqm) 2.5 3.0 3.8 pf input capacitance ( ck) 2.5 2.8 3.5 pf c o output capacitance (dq0 - dq15) 4.0 4.5 6.5 pf
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 35 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. dc electrical characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) symbol parameter min. max. units notes i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v -1 +1 m a 1 i o(l) output leakage current (d out is disabled, 0.0v v out v ddq ) -1 +1 m a v oh output level (lvttl) output ?h? level voltage ( iout = -2.0ma) 2.4 ? v v ol output level (lvttl) output ?l? level voltage (i out = +2.0ma) ? 0.4 v dc output load circuit output 1200 w 50pf 3.3 v 870 w v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 36 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents (t a = 0 to +70 c, v dd = 3.3v 0.3v) parameter symbol test condition speed units notes -7k -75 b -8b operating current i cc1 1 bank operation t rc = t rc (min), t ck = min active-precharge command cycling with- out burst operation 130 120 115 ma 1, 2, 3 precharge standby current in power down mode i cc2p cke v il (max), t ck = min, cs = v ih (min) 2 2 2 ma 1 i cc2ps cke v il (max), t ck = infinity, cs = v ih (min) 2 2 2 ma 1 precharge standby current in non-power down mode i cc2n cke 3 v ih (min), t ck = min, cs = v ih (min) 30 30 2 0 ma 1, 5 i cc2ns cke 3 v ih (min), t ck = infinity, 8 8 8 ma 1, 7 no operating current (active state: 4 bank) i cc3n cke 3 v ih (min), t ck = min, cs = v ih (min) 60 60 45 ma 1, 5 i cc3p cke v il (max), t ck = min, 6 6 6 ma 1, 6 operating current (burst mode) i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data, bl = 4 120 120 90 ma 1, 3, 4 auto (cbr) refresh current i cc5 t ck = min, t rc = t rc (min) cbr command cycling 175 175 155 ma 1 self refresh current i cc6 cke 0.2v sp 3 3 3 ma 1,8 lp 1.2 1.2 1.2 ma 8 1. currents given are valid for a single device. . 2. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input sig- nals are changed up to three times during t rc (min). 3. the specified values are obtained with the output open. 4. input signals are changed once during t ck (min). 5. input signals are changed once during three clock cycles. 6. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 7. input signals are stable . 8. sp : standard power ; lp : lower power
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 37 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) 1. an initial pause of 200 m s, with dqm and cke held high, is required after power-up. a precharge all banks command must be given followed by a minimum of two auto (cbr) refresh cycles before or after the mode register set operation. 2. the transition time is measured between v ih and v il (or between v il and v ih ) 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. load circuit a: ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.40v crossover point 5. load circuit a: ac measurements assume t t = 1.0ns. 6. load circuit b: ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.40v crossover point 7. load circuit b: ac measurements assume t t = 1.2ns. . ac characteristics d iagrams output input clock t oh t setup t hold t ac t lz 1.4v 1.4v 1.4v t t vtt = 1.4v output 50 w 50pf z o = 50 w ac output load circuit (a) t ckh t ckl output 50pf z o = 50 w ac output load circuit (b) v il v ih
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 38 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock and clock enable parameters symbol parameter -7 k -75b -8b units notes min. max. min. max. min. max. t ck3 clock cycle time, cas latency = 3 7 1000 7.5 1000 8 1000 ns t ck2 clock cycle time, cas latency = 2 7.5 1000 10 ? 10 1000 ns t ac3 (a) clock access time, cas latency = 3 ? ? ? ? ? ? ns 1 t ac2 (a) clock access time, cas latency = 2 ? ? ? ? ? ? ns 1 t ac3 (b) clock access time, cas latency = 3 ? 5.4 ? 5.4 ? 6 ns 2 t ac2 (b) clock access time, cas latency = 2 ? 5.4 ? 6 ? 6 ns 2 t ckh clock high pulse width 2.5 ? 2.5 ? 3 ? ns t ckl clock low pulse width 2.5 ? 2.5 ? 3 ? ns t ces clock enable set-up time 1.5 ? 1.5 ? 2 ? ns t ceh clock enable hold time 0.8 ? 0.8 ? 1 ? ns t sb power down mode entry time 0 7.5 0 7.5 0 10 ns t t transition time (rise and fall) 0.5 10 0.5 10 0.5 10 ns 1. access time is measured at 1.4v. see ac characteristics: notes 1, 2, 3, 4, 5 and load circuit a. 2. access time is measured at 1.4v. see ac characteristics: notes 1, 2, 3, 6, 7 and load circuit b. common parameters symbol parameter -7 k -75b -8b units notes min. max. min. max. min. max. t cs command setup time 1.5 ? 1.5 ? 2 ? ns t ch command hold time 0.8 ? 0.8 ? 1 ? ns t as address and bank select set-up time 1.5 ? 1.5 ? 2 ? ns t ah address and bank select hold time 0.8 ? 0.8 ? 1 ? ns t rcd ras to cas delay 15 ? 20 ? 20 ? ns 1 t rc bank cycle time 60 ? 67.5 ? 70 ? ns 1 t ras active command period 45 100k 45 100 k 50 100 k ns 1 t rp precharge time 15 ? 20 ? 20 ? ns 1 t rrd bank to bank delay time 15 ? 15 ? 20 ? ns 1 t ccd cas to cas delay time 1 ? 1 ? 1 ? ck 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). mode register set cycle symbol parameter -7k -75 b -8b units min. max. min. max. min. max. t rsc mode register set cycle time 15 ? 15 ? 20 ? ns
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 39 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. read cycle symbol parameter -7 k -75b -8b units notes min. max. min. max. min. max. t oh data out hold time ? ? ? ? 2.5 ? ns 1 2.7 ? 2.7 ? 3 ? ns 2, 4 t lz data out to low impedance time 0 ? 0 ? 0 ? ns t hz3 data out to high impedance time 3 5.4 3 5.4 3 6 ns 3 t hz2 data out to high impedance time 3 5.4 3 6 3 6 ns 3 t dqz dqm data out disable latency 2 ? 2 ? 2 ? ck 1. ac output load circuit a. 2. ac output load circuit b. 3. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 4. data out hold time with no load must meet 1.8ns (-75h, -75d, -75a). refresh cycle symbol parameter -7 k -75b -8b units notes min. max. min. max. min. max. t ref refresh period ? 64 ? 64 ? 64 ms 1 t srex self refresh exit time 10 ? 10 ? 10 ? ns 1. 8192 a uto refresh cycles. write cycle symbol parameter -7 k -75b -8b units min. max. min. max. min. max. t ds data in set-up time 1.5 ? 1.5 ? 2 ? ns t dh data in hold time 0.8 ? 0.8 ? 1 ? ns t dpl data input to precharge 15 ? 15 ? 20 ? ns t dal3 data in to active delay cas latency = 3 5 ? 5 ? 5 ? ck t dal2 data in to active delay cas latency = 2 5 ? 5 ? 5 ? ck t dqw dqm write mask latency 0 ? 0 ? 0 ? ck
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 40 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock frequency and latency symbol parameter -7k -75b -8b units f ck clock frequency 143 133 133 100 125 100 mhz t ck clock cycle time 7 7.5 7.5 10 8 10 ns t aa cas latency 3 2 3 2 3 2 ck t rp precharge time 3 2 3 2 3 2 ck t rcd ras to cas delay 3 2 3 2 3 2 ck t rc bank cycle time 9 8 9 7 9 7 ck t ras minimum bank active time 6 6 6 5 6 5 ck t dpl data in to precharge 2 2 2 2 2 2 ck t dal data in to active/refresh 5 5 5 5 5 5 ck t rrd bank to bank delay time 2 2 2 2 2 2 ck t ccd cas to cas delay time 1 1 1 1 1 1 ck t wl write latency 0 0 0 0 0 0 ck t dqw dqm write mask latency 0 0 0 0 0 0 ck t dqz dqm data disable latency 2 2 2 2 2 2 ck t csl clock suspend latency 1 1 1 1 1 1 ck
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 41 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. timing diagrams page ac parameters for write timing ................................................................................................................................ .. 42 ac parameters for read timing (3/3/3), bl=4 ........................................................................................................... 43 ac parameters for read timing (2/2/2), bl=2 ........................................................................................................... 44 ac parameters for read timing (3/2/2), bl=2 ........................................................................................................... 45 ac parameters for read timing (3/3/3), bl=2 ........................................................................................................... 46 mode register set ................................................................................................................................ ....................... 47 power on sequence and auto refresh (cbr) ............................................................................................................ 48 clock suspension / dqm during burst read ............................................................................................................. 49 clock suspension / dqm during burst write ............................................................................................................ 50 power down mode and clock suspend ...................................................................................................................... 51 auto refresh (cbr) ................................................................................................................................ ..................... 52 self refresh (entry and exit) ................................................................................................................................ ....... 53 random row read (interleaving banks) with precharge, bl=8 ................................................................................. 54 random row read (interleaving banks) with auto-precharge, bl=8 ........................................................................ 55 random row write (interleaving banks) with auto-precharge, bl=8 ........................................................................ 56 random row write (interleaving banks) with precharge, bl=8 ................................................................................. 57 read/write cycle ................................................................................................................................ ............... 58 interleaved column read cycle ................................................................................................................................ .. 59 auto precharge after a read burst, bl=4 ................................................................................................................... 60 auto precharge after a write burst, bl=4 ................................................................................................................... 61 burst read and single write operation ...................................................................................................................... 62 cs function (only cs signal needs to be asserted at minimum rate) ........................................................................ 63
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 42 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for write timing \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c e s t c s t c h t a s t r c d t d a l ? t d s a c t i v a t e c o m m a n d b a n k 0 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 0 w r i t e c o m m a n d b a n k 0 p r e c h a r g e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 0 t d h a x 0 a x 3 a x 2 a x 1 b x 0 b x 3 b x 2 b x 1 a y 0 a y 3 a y 2 a y 1 t c k 2 t c k h t c k l a c t i v a t e c o m m a n d b a n k 1 r a y c b x c a y r a y r b x r b x c a x r b y r b y r a z r a z r a x r a x t a h * b a 0 = ? l ? b a n k 2 , 3 = i d l e t r c t c e h t d p l ? t r p t r r d t d p l a n d t d a l d e p e n d o n c l o c k c y c l e t i m e a n d ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 2 ) ? s p e e d s o r t . s e e t h e c l o c k f r e q u e n c y a n d l a t e n c y t a b l e . a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 43 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/3/3) \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 0 h i - z a 1 0 a 0 - a 9 , t r c d t r a s a c t i v a t e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 0 t c k 3 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 t r c t a c 3 t o h b x 0 b x 1 c b x r a y r b x r b x r a y c a x r a x r a x * b a 0 = ? l ? r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 b e g i n a u t o p r e c h a r g e b a n k 0 b a n k 2 , 3 = i d l e t r p b x 2 b e g i n a u t o p r e c h a r g e b a n k 1 t r r d a x 3 a x 2 a x 1 a x 0 ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 44 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (2/2/2) \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 0 h i - z a 1 0 t c s t c h t c e h t a s t a h t r r d t r c d t r a s ( m i n ) t l z a c t i v a t e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 0 t c e s t c k 2 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 t r c t r p t a c 2 t o h t h z t c k h b x 0 b e g i n a u t o p r e c h a r g e b a n k 1 b x 1 t h z c b x r a y r b x r b x r a y c a x r a x r a x t c k l a x 0 a x 1 * b a 0 = ? l ? r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 b e g i n a u t o p r e c h a r g e b a n k 0 b a n k 2 , 3 = i d l e t r p n o t e : m u s t s a t i s f y t r a s ( m i n ) f o r - 2 6 0 : e x t e n d t r c d 1 c l o c k ( b u r s t l e n g t h = 2 , c a s l a t e n c y = 2 ; t r c d , t r p = 2 ) a 0 - a 9 , a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 45 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/2/2) \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 0 h i - z a 1 0 t c s t c h t c e h t a s t a h t r c d t l z a c t i v a t e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 0 t c k 3 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 t r p t a c 3 t o h t h z t c k h b x 0 b e g i n a u t o p r e c h a r g e b a n k 1 b x 1 t h z c b x r a y r b x r b x r a y c a x r a x r a x t c k l a x 0 a x 1 * b a 0 = ? l ? r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 b e g i n a u t o p r e c h a r g e b a n k 0 b a n k 2 , 3 = i d l e t r p t c e s n o t e : m u s t s a t i s f y t r a s ( m i n ) . e x t e n d e d t r c d 1 c l o c k . n o t r e q u i r e d f o r b l 3 4 . t r r d t r a s t r c ( b u r s t l e n g t h = 2 , c a s l a t e n c y = 3 ; t r c d , t r p = 2 ) a 0 - a 9 , a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 46 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/3/3) \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 0 h i - z a 1 0 a 0 - a 9 , t r r d t r c d t r a s ( m i n ) a c t i v a t e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 0 t c k 3 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 t r c t r p t a c 3 t o h b x 0 b e g i n a u t o p r e c h a r g e b a n k 1 b x 1 c b x r a y r b x r b x r a y c a x r a x r a x r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 b e g i n a u t o p r e c h a r g e b a n k 0 t r p a x 0 a x 1 n o t e : m u s t s a t i s f y t r a s ( m i n ) . e x t e n d e d t r c d n o t r e q u i r e d f o r b l 3 4 . t c e h a 1 1 , a 1 2 t 1 4 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 2 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 )
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 47 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. mode register set \ c k c k e c s d q r a s c a s w e b a 0 , b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 , a 1 1 , a 0 - a 9 p r e c h a r g e c o m m a n d a l l b a n k s m o d e r e g i s t e r s e t c o m m a n d a n y c o m m a n d a d d r e s s k e y t r p t c k 2 t r s c ( c a s l a t e n c y = 2 ) a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 48 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. power-on sequence and auto refresh (cbr) \ c k c k e c s d q r a s c a s w e b s d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , p r e c h a r g e c o m m a n d a l l b a n k s t r p m i n i m u m o f 8 r e f r e s h c y c l e s a r e r e q u i r e d 1 s t a u t o r e f r e s h c o m m a n d t r c h i g h l e v e l i s r e q u i r e d 8 t h a u t o r e f r e s h c o m m a n d i n p u t s m u s t b e s t a b l e f o r 2 0 0 m s t c k a n y c o m m a n d 2 c l o c k m i n . m o d e r e g i s t e r a d d r e s s k e y s e t c o m m a n d a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 49 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock suspension / dqm during burst read \ c k c k e c s d q r a s c a s w e d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , r a x a x 0 a x 1 a x 2 a x 3 a c t i v a t e c o m m a n d b a n k 0 c l o c k s u s p e n d 2 c y c l e s c l o c k s u s p e n d 1 c y c l e c l o c k s u s p e n d 3 c y c l e s r a x r e a d c o m m a n d b a n k 0 c a x t h z t c k 3 * b a 1 a x 4 a x 6 a x 7 t c e s t c e h * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 50 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. clock suspension / dqm during burst write \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , r a x a c t i v a t e c o m m a n d b a n k 0 r a x c a x d a x 0 c l o c k s u s p e n d 1 c y c l e d a x 1 d a x 2 c l o c k s u s p e n d 2 c y c l e s c l o c k s u s p e n d 3 c y c l e s w r i t e c o m m a n d b a n k 0 t c k 3 d a x 5 d a x 6 d a x 7 d a x 3 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 51 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. power down mode and clock suspend \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c e s t c e s v a l i d c a x r a x r a x a x 2 a x 0 a x 1 a x 3 a c t i v a t e c o m m a n d b a n k 0 n o p r e a d c o m m a n d b a n k 0 a c t i v e s t a n d b y c l o c k s u s p e n s i o n s t a r t c l o c k s u s p e n s i o n e n d p r e c h a r g e c o m m a n d b a n k 0 p r e c h a r g e s t a n d b y t h z a n y c o m m a n d t c k 2 t c e s t s b n o p * b a 0 = ? l ? b a n k 2 , 3 = i d l e t s b ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 2 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 52 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. auto refresh (cbr) \ c k c k e c s d q r a s c a s w e b s d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , p r e c h a r g e c o m m a n d a u t o r e f r e s h c o m m a n d a u t o r e f r e s h c o m m a n d t r c t r p t r c t c k 2 a l l b a n k s ( c a s l a t e n c y = 2 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 53 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. self refresh (entry and exit) \ c k c k e c s d q r a s c a s w e b s d q m t 2 t 3 t 4 t 0 t 1 h i - z a 1 0 a l l b a n k s m u s t b e i d l e s e l f r e f r e s h e n t r y a 0 - a 9 , t m t m + 2 t m + 3 t m + 4 t m + 5 t m + 1 t m + 7 t m + 8 t m + 9 t m + 1 0 t m + 6 t m + 1 3 t m + 1 1 t m + 1 2 t m + 1 5 t m + 1 4 t c e s t s b a n y c o m m a n d t c e s t r c t s r e x s e l f r e f r e s h e x i t p o w e r d o w n e n t r y p o w e r d o w n e x i t ( n o t e : t h e c k s i g n a l m u s t b e r e e s t a b l i s h e d p r i o r t o c k e r e t u r n i n g h i g h . ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 54 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. random row read (interleaving banks) with precharge \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , c b y r e a d c o m m a n d b a n k 1 b y 0 t c k 3 h i g h t a c 3 a c t i v a t e c o m m a n d b a n k 1 r b x r b x a c t i v a t e c o m m a n d b a n k 0 r a x r a x c b x r e a d c o m m a n d b a n k 1 a c t i v a t e c o m m a n d b a n k 1 r b y r b y t r c d p r e c h a r g e c o m m a n d b a n k 1 c a x r e a d c o m m a n d b a n k 0 b x 0 b x 1 b x 2 b x 3 b x 4 b x 5 b x 6 a x 0 a x 1 a x 4 a x 5 a x 6 a x 7 p r e c h a r g e c o m m a n d b a n k 0 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 55 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. random row read (interleaving banks) with auto-precharge \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , c b y b y 0 t c k 3 h i g h t a c 3 a c t i v a t e c o m m a n d b a n k 1 r b x r b x a c t i v a t e c o m m a n d b a n k 0 r a x r a x c b x a c t i v a t e c o m m a n d b a n k 1 r b y r b y t r c d c a x b x 0 b x 1 b x 2 b x 3 b x 4 b x 5 b x 6 b x 7 a x 0 a x 4 a x 5 a x 6 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 a x 1 s t a r t a u t o p r e c h a r g e b a n k 1 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 s t a r t a u t o p r e c h a r g e b a n k 0 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 * b a 0 = ? l ? b a n k 2 , 3 = i d l e r a x r a x a x 7 ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 56 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. random row write (interleaving banks) with auto-precharge \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 3 h i g h d a x 0 d a x 1 d a x 4 d a x 7 d a x 6 d a x 5 d b x 0 d b x 3 d b x 2 d b x 1 d b x 4 d b x 5 d a y 2 d a y 1 d a y 0 c a x a c t i v a t e c o m m a n d b a n k 0 r a x r a x a c t i v a t e c o m m a n d b a n k 1 r b x r b x a c t i v a t e c o m m a n d b a n k 0 r a y r a y c b x c a y t r c d d b x 7 d b x 6 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 * b a 0 = ? l ? b a n k 2 , 3 = i d l e t d a l ? t d a l ? ? n u m b e r o f c l o c k s d e p e n d s o n c l o c k c y c l e t i m e a n d s p e e d s o r t . s e e t h e c l o c k f r e q u e n c y a n d l a t e n c y t a b l e . b a n k m a y b e r e a c t i v a t e d a t t h e c o m p l e t i o n o f t d a l . ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 57 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. random row write (interleaving banks) with precharge \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 3 h i g h d a x 0 d a x 1 d a x 4 d a x 7 d a x 6 d a x 5 d b x 0 d b x 3 d b x 2 d b x 1 d b x 4 d b x 5 d a y 2 d a y 1 d a y 0 w r i t e c o m m a n d b a n k 0 c a x a c t i v a t e c o m m a n d b a n k 0 r a x r a x a c t i v a t e c o m m a n d b a n k 1 r b x r b x a c t i v a t e c o m m a n d b a n k 0 r a y r a y c b x w r i t e c o m m a n d b a n k 1 p r e c h a r g e c o m m a n d b a n k 0 w r i t e c o m m a n d b a n k 0 c a y p r e c h a r g e c o m m a n d b a n k 1 t r p t r c d d b x 7 d b x 6 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) t d p l a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 58 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. read / write cycle \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 3 w r i t e c o m m a n d b a n k 0 c a y d a y 0 d a y 1 d a y 3 a x 0 a x 1 a x 3 a x 2 t h e w r i t e d a t a i s m a s k e d w i t h a z e r o c l o c k l a t e n c y t h e r e a d d a t a i s m a s k e d w i t h a t w o c l o c k l a t e n c y a c t i v a t e c o m m a n d b a n k 0 r a x r a x c a x r e a d c o m m a n d b a n k 0 d a y 4 p r e c h a r g e c o m m a n d b a n k 0 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 8 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 59 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. interleaved column read cycle \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 3 t r c d t a c 3 c b y r e a d c o m m a n d b a n k 1 c b z r e a d c o m m a n d b a n k 1 c a y p r e c h a r g e c o m m a n d b a n k 1 a x 0 a x 3 a x 2 a x 1 b x 0 b y 1 b y 0 b x 1 b z 0 b z 1 a y 0 a y 3 a y 2 a y 1 a c t i v a t e c o m m a n d b a n k 0 r a x r a x c b x r e a d c o m m a n d b a n k 1 c a x a c t i v a t e c o m m a n d b a n k 1 r e a d c o m m a n d b a n k 0 r b x r b x r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 s t a r t a u t o p r e c h a r g e b a n k 0 * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 60 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. auto precharge after read burst \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 3 h i g h r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 c b y s t a r t a u t o p r e c h a r g e b a n k 1 s t a r t a u t o p r e c h a r g e b a n k 0 a x 3 a x 2 a x 0 a x 1 b x 3 b x 2 b x 0 b x 1 a y 3 a y 2 a y 0 a y 1 a c t i v a t e c o m m a n d b a n k 0 r a x r a x r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 c b x r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 a c t i v a t e c o m m a n d b a n k 1 r b x c a x r b x a c t i v a t e c o m m a n d b a n k 1 r e a d c o m m a n d b a n k 0 r b y c a y r b y b y 0 b y 1 * b a 0 = ? l ? b a n k 2 , 3 = i d l e s t a r t b a n k 1 a u t o p r e c h a r g e ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 3 ; t r c d , t r p = 3 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 61 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. auto precharge after write burst \ c k c k e c s d q r a s c a s w e * b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 a 0 - a 9 , t c k 2 h i g h w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 c b y a c t i v a t e c o m m a n d b a n k 1 r b x r b x w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 1 c b x d a x 3 d a x 2 d a x 1 d a x 0 d b x 3 d b x 2 d b x 1 d b x 0 d a y 3 d a y 2 d a y 1 d a y 0 d b y 3 d b y 2 d b y 1 d b y 0 d a z 3 d a z 2 d a z 1 d a z 0 a c t i v a t e c o m m a n d b a n k 0 r a z r a z w r i t e c o m m a n d b a n k 0 c a x w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 c a y a c t i v a t e c o m m a n d b a n k 1 r b y r b y a c t i v a t e c o m m a n d b a n k 0 r a x r a x w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k 0 c a z * b a 0 = ? l ? b a n k 2 , 3 = i d l e a 1 1 , a 1 2 t d a l ? t d a l ? ? n u m b e r o f c l o c k s d e p e n d s o n c l o c k c y c l e a n d s p e e d s o r t . s e e t h e c l o c k f r e q u e n c y a n d l a t e n c y t a b l e . b a n k m a y b e r e a c t i v a t e d a t t h e c o m p l e t i o n o f t d a l . t d a l ? ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 2 )
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 62 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. burst read and single write operation \ c k c k e c s d q 0 - d q 7 r a s c a s w e * b a 1 l d q m a 1 0 a 0 - a 9 , d q 8 - d q 1 5 u d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z t c k 2 a c t i v a t e c o m m a n d b a n k 0 r a v r a v c a v r e a d c o m m a n d b a n k 0 s i n g l e w r i t e c o m m a n d b a n k 0 c a w h i g h c a y r e a d c o m m a n d b a n k 0 a v 0 d a w 0 h i - z a v 2 a v 1 a v 3 d a x 0 a v 2 a v 1 a y 2 d a w 0 a y 0 a y 3 a v 0 a v 3 s i n g l e w r i t e c o m m a n d b a n k 0 a y 3 s i n g l e w r i t e c o m m a n d b a n k 0 d a z 0 d a z 0 c a x c a z l o w e r b y t e i s m a s k e d a y 0 a y 1 u p p e r b y t e i s m a s k e d l o w e r b y t e i s m a s k e d * b a 0 = ? l ? b a n k 2 , 3 = i d l e ( b u r s t l e n g t h = 4 , c a s l a t e n c y = 2 ) a 1 1 , a 1 2
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 63 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. cs function (only cs signal needs to be asserted at minimum rate) \ c k c k e c s d q r a s c a s w e b a 0 , b a 1 d q m t 2 t 3 t 4 t 0 t 1 t 6 t 7 t 8 t 9 t 5 t 1 1 t 1 2 t 1 3 t 1 4 t 1 0 t 1 6 t 1 7 t 1 8 t 1 9 t 1 5 t 2 2 t 2 0 t 2 1 h i - z a 1 0 , a 1 2 a 0 - a 9 , a 1 1 t c k 3 r a x l o w r a x c a x c a y r e a d c o m m a n d b a n k a w r i t e c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k a p r e c h a r g e c o m m a n d b a n k a a x 0 d a y 0 d a y 3 d a y 2 d a y 1 a x 3 a x 2 a x 1 t r c d t d p l ( a t 1 0 0 m h z b u r s t l e n g t h = 4 , c a s l a t e n c y = 3 , t r c d , t r p = 3 )
nt5sv64m4at(l) nt5sv32m8at(l) nt5sv16m16at(l) 256mb synchronous dram rev 1.0 may, 2001 64 ? nanya technology corp . all rights reserved. nanya technology corp. reserves the right to change products and specifications without notice. package dimension s ( 400mil; 54 lead; thin small outline package) lead #1 0.80 basic 0.35 1 0 . 1 6 0 . 1 3 22.22 0.13 1 1 . 7 6 0 . 2 0 - 0.05 + 0.10 0.71ref detail a 0.10 seating plane detail a 0.5 0.1 0.05 min 1 . 2 0 m a x 0.25 basic gage plane
nanya technology corporation. all rights reserved. printed in taiwan, r.o.c. may 2001 the following are trademarks of nanya technology corporation in r.o.c , or other countries, or both. nanya nanya logo other company, product and service names may be trademarks or services maeks of others. nanya technology corporation (ntc) reserves the right to make changes without notice. ntc warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ntc?s standard warranty. testing and other quality control techniques are utilize to the extent ntc deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). ntc semiconductor products are not designed, intend, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of ntc products in such applications is understood to be fully at the risk of the customer. use of ntc products in suc h applications requires the written approval of an appropriate ntc officer. question concerning potential risk applications should be directed to ntc through a local sales office. in order to minimize risks associated with the customer?s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. ntc assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ntc warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ntc covering or relating to any combinatio n, machine, or process in which such semiconductor products or services might be or are used. nanya technology corporation hwa ya technology park 669, fu hsing 3rd rd., kueishan, taoyuan, taiwan, r.o.c. the nanya technology corporation home page can be found at http:\\www.nanya.com ? ?

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